As specifications grow to hundreds of pages, traditional verification workflows struggle to maintain consistency, traceability, and speed. This session demos Normal EDA, which replaces subjective, hand-written flows with NormML - a proprietary formal language that ingests raw specs, timing diagrams, and existing testbenches to build an auditable graph that auto-generates zero-to-one test plans, SystemVerilog/UVM stimulus, and traceable coverage links. The system reasons across multimodal data to flag inconsistencies before RTL reaches the simulator, slashing coverage closure time.
Maxim Khomiakov
Maxim Khomiakov, PhD, is a Senior AI Engineer at Normal Computing, building reliable, high‑performance AI software for automating chip verification and design. He previously developed and deployed production-scale machine learning models within Apple Maps. Before that, he led data science efforts at Otovo and co‑founded Sunmapper (acquired by Otovo). Maxim holds a PhD in Machine Learning from the Technical University of Denmark (DTU).