Distributed training jobs are brittle; a single node failure can halt progress and waste expensive GPU cycles. This technical demo dives into Cluster Director, focusing on how engineers can automate resilient, large-scale GPU infrastructure. We'll start with a declarative YAML configuration to define and provision a multi-node GPU cluster, optimized with the ideal network topology for NCCL communication. The core of the demo will be a live failure simulation. You will see Cluster Director automatically detect a preempted node, perform remediation, and maintain the integrity of the running workload with minimal disruption.

Large language models can now power capable software agents, yet real‑world success comes from disciplined engineering rather than flashy frameworks. Most reliable agents are built from simple, composable patterns instead of heavy abstractions.

The talk will introduce patterns to add complexity and autonomy only when it pays off. Attendees should leave with a practical decision framework for escalating from a single prompt to multi‑step agents, also keeping in mind guardrails for shipping trustworthy, cost‑effective agents at scale. 

Revterra’s Kinetic Stabilizer is engineered to handle the massive and volatile power swings demanded by large-scale AI workloads. AI is bottlenecked by infrastructure and requires a rapidly scalable, high-performance power quality solution that can be deployed without fear of supply chain disruption. Our battery-free technology provides a stable bridge between the grid and AI loads with a physically instantaneous, passive response—no power electronics required. Unlike conventional solutions, the Kinetic Stabilizer offers unmatched cost-effectiveness on a per-kW basis and a functionally infinite cycle life, free from the constraints of chemical storage.

Flexnode’s approach delivers a strategic advantage over traditional data center construction by transferring complexity off the job site and into a controlled manufacturing environment. Our modules are engineered for speed, scalability, and geographic flexibility—purpose built to support the rapidly evolving demands of AI and high-performance compute workloads. By industrializing the data center, we ensure repeatable, high-quality outcomes that can be rapidly deployed with minimal on-site work.

AI is transforming not just what chips can do, but how we design them. This panel of top investors and semiconductor leaders will explore how AI is accelerating chip development, lowering barriers to entry, and expanding who can participate in the next era of hardware innovation.

AI is emerging as a true collaborator—capable of reasoning through design trade-offs, iterating architectures, and navigating verification alongside human engineers. This comes at a time when chip development is costly and complex, often taking 3–5 years and over $100M, with a looming shortage of 1 million skilled workers by 2030. Startups face even higher hurdles compared to industry giants with vast data and teams. Can AI level the playing field and make chip creation faster, cheaper, and more accessible?

As AI algorithms become more complex, they consume disproportionately greater run-time and energy. This makes meeting performance or efficiency goals require some level of hardware acceleration. The highest levels of performance and efficiency are achieved with custom hardware. Traditional hardware design and verification methodologies are labor-intensive and time-consuming and are not a good match for rapidly evolving AI technologies.

We will introduce the application of High-Level Synthesis (HLS) for automating many of the hardware design tasks involved in creating a bespoke accelerator. Using HLS, popular machine learning frameworks, and Quantize-Aware Training, we can build highly optimized and bit precise hardware, targeting ASIC or FPGA implementations.